Compact Keccak Hardware Architecture for Data Integrity and Authentication on FPGAs

SAN İ., AT N.

INFORMATION SECURITY JOURNAL, cilt.21, sa.5, ss.231-242, 2012 (ESCI) identifier identifier

  • Yayın Türü: Makale / Tam Makale
  • Cilt numarası: 21 Sayı: 5
  • Basım Tarihi: 2012
  • Doi Numarası: 10.1080/19393555.2012.660678
  • Dergi Adı: INFORMATION SECURITY JOURNAL
  • Derginin Tarandığı İndeksler: Emerging Sources Citation Index (ESCI), Scopus
  • Sayfa Sayıları: ss.231-242
  • Anahtar Kelimeler: compact hardware design, coprocessor approach, FPGA, Keccak, authentication
  • Anadolu Üniversitesi Adresli: Evet

Özet

Cryptographic hash functions play a crucial role in networking and communication security, including their use for data integrity and message authentication. Keccak hash algorithm is one of the finalists in the next generation SHA-3 hash algorithm competition. It is based on the sponge construction whose hardware performance is worth investigation. We developed an efficient hardware architecture for the Keccak hash algorithm on Field-Programmable Gate Array (FPGA). Due to the serialization exploited in the proposed architecture, the area needed for its implementation is reduced significantly accompanied by higher efficiency rate. In addition, low latency is attained so that higher operating frequencies can be accessed. We use the coprocessor approach which exploits the use of RAM blocks that exist in most FPGA platforms. For this coprocessor, a new datapath structure allowing parallel execution of multiple instructions is designed. Implementation results prove that our Keccak coprocessor achieves high performance in a small area.