An Efficient Low Area Implementation of 2-D DCT on FPGA

DOĞAN A.

9th International Conference on Electrical and Electronics Engineering (ELECO), Bursa, Turkey, 26 - 28 November 2015, pp.771-775 identifier

  • Publication Type: Conference Paper / Full Text
  • City: Bursa
  • Country: Turkey
  • Page Numbers: pp.771-775
  • Anadolu University Affiliated: Yes

Abstract

This paper presents the design and implementation for 2-D discrete cosine transform (DCT) with the goal of achieving low area utilization and high-speed operation on FPGAs. The design is based on the row-column decomposition technique, which requires two successive 1-D DCT transforms and a transpose memory between them for storing and transposing the results of the first 1-D DCT. The proposed implementation of 2-D DCT is capable of compressing at least 70 images per second in 720x480 resolution on Xilinx Spartan 3E and 30 images per second in 1920x1080 resolution on Xilinx Virtex 7 FPGA. Consequently, the proposed 2-D DCT design and implementation can be very useful in various image and video compressing applications.