A low-area unified hardware architecture for the AES and the cryptographic hash function Grostl

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AT N., Beuchat J., Okamoto E., SAN İ., Yamazaki T.

JOURNAL OF PARALLEL AND DISTRIBUTED COMPUTING, vol.106, pp.106-120, 2017 (SCI-Expanded) identifier identifier

  • Publication Type: Article / Article
  • Volume: 106
  • Publication Date: 2017
  • Doi Number: 10.1016/j.jpdc.2017.01.029
  • Journal Indexes: Science Citation Index Expanded (SCI-EXPANDED), Scopus
  • Page Numbers: pp.106-120
  • Keywords: Embedded systems, Coprocessors, Field programmable gate arrays, Cryptographic hash functions, Ciphers, Cryptography, SECURITY
  • Anadolu University Affiliated: Yes


This article describes the design of a compact 8-bit coprocessor for the Advanced Encryption standard (AES) (encryption, decryption, and key expansion) and the cryptographic hash function Grostl. Our Arithmetic and Logic Unit has only one instruction that allows for implementing AES encryption, AES decryption, AES key expansion, and Grostl at all levels of security (i.e. 128-, 192-, and 256-bit encryption keys; 256- and 512-bit message digests). A fully autonomous implementation of Grostl and AES on a Virtex-6 FPGA requires 169 slices and a single 36k memory block, and achieves a competitive throughput (up to 217 Mbits/s and 92 Mbits/s for encryption and hashing, respectively). The proposed coprocessor is well-suited for resource-constrained embedded systems, where several security protocols rely only on block ciphers and hash functions. One can exploit the design philosophy presented in this paper in order to design a unified architecture for other algorithms. (C) 2017 Elsevier Inc. All rights reserved.